To perform the USB communication the user must call. USBBlaster.begin ( bool statusled) If statusled is true the builtin LED will show the programmers activity. hex files is a bit awkward, but after doing it one, two times it should be fine, it should be described in the example.ĭo you want to select the loaded image via GPIO or via internal configuration, because if you chose internal, your working design has to be able to switch back to your golden image. This will create a composite USB device mocking the original Blaster VID/PID so Quartus can happily use it as a programmer/debugger without any patching. Be sure to protect your flash adresses the image resides.Īdd a JTAG connection on your board (config guide Max10) and program the FPGA before he goes out of the house. Here's a documentation for Remote System Upgrade with UART. You can read about its flash memory here.Ĭreate a golden image, which is capable of writing the working image into flash.

Max10 supports dual-compressed image mode. You need: for first time programming: QuartusII, QSYS, NIOS SBT, JTAG connection to your FPGA and for remote upgrade: a terminal programm which is capable to send files and UART connection to your FPGA. This is more of a guide how it could be done.

One of the answers suggested a bootloader-style scheme (which is also suggested in this video, but I am using one of the devices that support single configuration only.

If you have flashed a bistream to a MAX10 using non-Altera programming hardware and standard Altera/Quartus programming software.

If you have flashed a bitstream to a MAX10 using a USB Blaster using non-Altera software or.

MAXII) with non-Altera software+hardware

If you have flashed a bitstream to another Altera flash-based FPGA (e.g.

If you know how to do any of the following, I will upvote any of the following in the hope of putting together a complete solution from the individual pieces: I can do whatever software and hardware kludges are required.

What considerations need to be given to hardware design to enable this functionality? (For example, can GPIOs be used to bit-bang JTAG - an ideal solution from a cost perspective - or do I need a chip like a an FTDI)įor the purposes of developing a proof-of-concept solution, I have a MAX10 Eval kit and a BeagleBone Black.

What software tools can be used for this purpose? ( fpga_manager does not yet seem prime-time, and urjtag does not have much in the way of recent Altera support).

Since we would like to design to be field upgradeable, we need to a solution to upload a bitstream to the flash of the MAX10 from Linux (the embedded OS) without a USB Blaster or the Quartus programming tools (since it's an ARM board, we can't run the binaries). Up until now, I have been using the standard Altera tools for development ( Quartus Prime and USB Blaster as the programming software and hardware tools), but once the product ships, we don't have this option. I am currently using the flash-based Altera MAX10 in designed attached to main processor which runs Linux on a custom board (the FPGA itself just implements a few peripherals the processor running Linux is a normal ARM design).

Altera usb blaster linux